module Z80::Program::Mnemonics

Z80 Mnemonics¶ ↑

All Z80 instructions are created as singleton methods. They produce machine code which is added to the Program class instance variable: Program.code.

These mnemonics mimic standard ones (used in assemblers) but with some exceptions (because of ruby parser spec.):

• all instruction and register names are lower case

• all conditions are upper case e.g.:

  jp NZ, somewhere
  

  use [ ] instead of ( ) e.g.:

  ld a, [de]
  ex [sp], hl
  ld [ix+index], c
  ld a, [label_name]
  

• use anda instead of and

• use ora instead of or

• use inp instead of in

• use ex af,af instead of ex af,af' (no apostrophe after af')

• do not use [ ] around out and inp instructions' arguments e.g.:

  out c, a        # ok
  out (c), a      # () are ok here
  inp a, (0xfe)
  inp a, (io.ula)
  

• do not use [ ] around JP (HL/IX/IY) e.g.:

  jp  hl     # ok
  jp  (hl)   # () are ok
  

Undocumented (by Zilog) Z80 instructions¶ ↑

See: www.z80.info/z80undoc.htm

• sll (or sl1) which means shift left (a b c d e h l [hl] [ixn]) by one and set it's bit 0 to 1

• 2 in 1 instructions like

  set 4, [ix+n], b
  

  which means:

  set 4, [ix+n]; ld b, [ix+n]
  

  but is a single instruction only. It applies to ix/iy indexing registers and following instructions (without bit):

  rlc rrc rl rr sla sra sll srl set res
  

• ixh/ixl/iyh/iyl 8-bit registers of 16bit ix/iy use them replacing l and h registers in:

  ld inc dec add adc sbc sub anda xor ora cp
  

  however you can't mix (ixh ixl)/(iyh iyl)/h/l registers in one instruction like:

  ld ixh, iyh # invalid
  ld h, iyh   # invalid
  

• and some less useful but included for completeness:

  out (c)    # output to (BC) port 0 or 255 depending on the CPU manufacturer
  inp (c)    # sets flags, but drops the value
  

A list of Mnemonics¶ ↑

adc add anda bit call ccf cp cpd cpdr cpi cpir cpl daa dec di djnz ei ex exx halt hlt im0 im01 im1 im2 inc ind indr ini inir inp jp jr ld ldd lddr ldi ldir neg nop ora otdr otir out outd outi pop push res ret reti retn rl rla rlc rlca rld rr rra rrc rrca rrd rst sbc scf set sl1 sla sll sra srl sub xor